[elektro] VHDL kivonas, ido

[uprogc]

Egy allapota nem volt leirva az if-nek.....Hm.

On Tue, Nov 6, 2018 at 7:36 PM uprogc <uprogc at gmail.com> wrote:

> Udv,
>
> Ez mekkora baj es konkretan mit jelent ?
>
> Warning: VHDL Process Statement warning at dc_fifo_manage.vhd(146):
> inferring latch(es) for signal or variable "ovr", which holds its previous
> value in one or more paths through the process
>
>