[elektro] VHDL kivonas, ido

uprogc uprogc at gmail.com
Tue Nov 6 18:36:06 CET 2018


Udv,

Ez mekkora baj es konkretan mit jelent ?

Warning: VHDL Process Statement warning at dc_fifo_manage.vhd(146):
inferring latch(es) for signal or variable "ovr", which holds its previous
value in one or more paths through the process


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