Verilog kerdes

[Fuzesi Arnold]

http://www.synplicity.com/literature/pdf/Verilog_%202001.pdf
7 oldal...ez kell?

Regebbi verilog ezekszerint nem tamogatja a "generate statements"-et.

http://www.angelfire.com/in/rajesh52/verilogvhdl.html

Structural replication
VHDL. The generate statement replicates a number of instances of the same 
design-unit or some sub part of a design, and connects it appropriately.
Verilog. There is no equivalent to the generate statement in Verilog.


Arnold
----- Original Message ----- 
From: "hoyuka" <hoyuka at c2.hu>
To: <elektro at tesla.hu>
Sent: Tuesday, January 17, 2006 1:16 AM
Subject: Re: Verilog kerdes


> Szia!
>
> Kiprobaltam igy:
>
>    integer i;
>    for(i=0;i<7;i=i+1) begin
>        PWM pwm[i](clk, PWM_In[i], PWM_Bus[i]);
>    end
>
> Ezt nem eszi meg. Ehhez hasonlo "peldanyositast" C/C++ nyelvekben sem
> lehet csinalni.
> Tehat a kerdes meg nyitott.
> Eloszor! Masodszor! Senki tobbet harmadszor ?!?!
>
>
> udv.
> hoyuka
>
>
>> From: BEREGNYEI Balazs <bereg at impulzus.sch.bme.hu>
>> Date: Jan 16, 2006 11:56 PM
>> Subject: Re: Verilog kerdes
>> To: elektro at tesla.hu
>>
>>
>>
>> On Mon, 16 Jan 2006, hoyuka wrote:
>>
>>> PWM       pwm7(clk, PWM_In[7], PWM_Bus[7]),
>>>    pwm6(clk, PWM_In[6], PWM_Bus[6]),
>>>    pwm5(clk, PWM_In[5], PWM_Bus[5]),
>>>    pwm4(clk, PWM_In[4], PWM_Bus[4]),
>>>    pwm3(clk, PWM_In[3], PWM_Bus[3]),
>>>    pwm2(clk, PWM_In[2], PWM_Bus[2]),
>>>    pwm1(clk, PWM_In[1], PWM_Bus[1]),
>>>    pwm0(clk, PWM_In[0], PWM_Bus[0]);
>>>
>>> A kerdes megegyszer: Hogyan lehetne a modult 8 peldanyban letrehozni,
>>> egyetlen sorban?
>>
>> Tippelek: for ciklussal. Verilogban meg soha nem hasznaltam, de tudok
>> rola, hogy van :-)
>>
>> BB
>>
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>>
>>
>> --
>> http://hoyuka.myip.hu
>>
>
> -- 
> http://hoyuka.myip.hu
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