[elektro] CTMU setup

[Kovács Kenéz]

Hali!

Mutasson valaki egy mintát PIC18F24KA302-re, CTMU beállításra az AN0 lábra. (MPLAB C30) Nagyon megköszönném .

2. este küzdök vele sikertelenül.
Debugolva sem látok semmilyen áramgenerátoros töltést az AN0-ra kötött kondin !
(Neten nem találtam mintát kifejezetten erre a proc.-ra.)
(A fene aki megeszi az ilyen "repülővizsgás" ezer regiszteres beállításokat !!)

Jelenlegi kód, ami nem megy:

***************** CTMU beállítás *****************

//CTMUCON1 - CTMU Control register
  CTMUCON1 = 0;
  _CTMUEN = 1;       // CTMU disabled
  _CTMUSIDL = 1;     // continue operation in idle mode
  _TGEN     = 0;     // dis. edge delay generation
  _EDGEN    = 1;     // Edge are en.
  _EDGSEQEN = 0;     // No edge sequence is needed
  _IDISSEN  = 0;     // Analog current source output is not grounded
  _CTTRIG   = 0;     // Trigger output is disabled 
  // CTMUCON2 
  CTMUCON2 = 0;
  _EDG1EDGE = 0;     // input is level-sensitive (=1, input is edge-sensitive  
  _EDG1POL  = 1;     // Edge 1 is programmed for a positive edge response
  _EDG1SEL  = 0;     // Edge 1 source is Timer1
  _EDG2     = 0;     // Edge 2 has not occurred
  _EDG1     = 0;     // Edge 1 has not occurred
  _EDG2EDGE = 0;     // input is level-sensitive (=1, input is edge-sensitive  
  _EDG2POL  = 1;     // Edge 2 is programmed for a positive edge     
  _EDG2SEL  = 0;     // Edge 2 source is Timer1
  //CTMUICON - CTMU Current Control Register
  CTMUICON = ((unsigned int)(isrc << 8)) + ((unsigned int)(itrim << 10)); 





***************- 12 bites A/D beállítás RA0 - AN0 pin *******************************
  ANSELA    = 0;
  ANSELB    = 0;
  // AN0-RA0
  TRISA |= 1;	     // input
  _ANSA0  = 1;       // analog input pin
  //
  // AD1CON1 -----------------------------------------
 _ADON   = 0;               // ADC OFF
 _ADSIDL = 0;               // 0 = Continue module operation in Idle mode
 _FORM   = 0;               // 00 = Absolute decimal result, unsigned, right-justified
 _SSRC   = 0;               // 0000 = The SAMP bit must be cleared by software
 _ASAM   = 0;               // 0 = Sampling begins when SAMP bit is manually set
 // AD1CON2 -----------------------------------------
 AD1CON2 = 0;
 _PVFCG  = 0;               // 00 =AVDD Positive Voltage Reference
 _NVCFG  = 0;               // 0 =AVSS Negative Voltage Reference 
 _BUFREGEN = 0;             // 0 = A/D result buffer is treated as a FIFO
 _CSCNA  = 0;               // 0 = not Scan inputs 
 _SMPI   = 0;
 _ALTS   = 0;               // 0 = Always uses channel input selects for SAMPLE A
 // AD1CON3
 _ADRC   = 0;               // 0 = Clock derived from system clock
 _SAMC   = 8;               // 0 = 0 Tad auto sample time
 _ADCS   = 4;               // 4 Tcy = 1 Tad  (32 MHz)
 // AD1CON5
 _ASENA  = 0;               // 0 =  Auto-Scan is disabled
 _LPENA  = 0;               // 0 =  Full power enabled after scan
 //
 _CTMUREQ = 1;              // 1 =  CTMU is enabled when the ADC is enabled and active
 _BGREQ  = 0;               // 0 =  Band gap is not enabled by the ADC
 //_VRSREQ = 0;               // 0 =  On-chip regulator is not enabled by the ADC
 _ASINTMD  = 0;             // 00 = No interrupt Auto-Scan (Threshold Detect) Interrupt Mode bits
 _WM     = 0;               // 00 = Legacy operation (conversion data saved to location determined by buffer register bits)
 _CM0 = 0; _CM1 = 0;        // Compare Mode bits
 // AD1CHS  A/D Sample Select Register
  _CH0NB  = 0;               // 3 bit, Sample B Channel 0 Negative Input Select bits
  _CH0SB  = 0;               // 5 bit, S/H Amplifier Positive Input Select for MUX B Multiplexer Setting bits
  _CH0NA  = 0;               // 3 bit, 000 = AVSS, Sample A Channel 0 Negative Input Select bits
  _CH0SA  = 0b00010001;    // 5 bit, (CTMU select) Sample A Channel 0 Positive Input Select bits
  // AD1CHITH
  AD1CHITH = 0;
  // AD1CHITL
  AD1CHITL = 0;
  // AD1CSSH   A/D Input Scan Select Register (High Word)
  AD1CSSH    = 0;            // no scanning required
  // AD1CSSL:  A/D Input Scan Select Register (Low Word)
  AD1CSSL    = 0;            // no scanning required
  // AD1CTMENH  CTMU Enable Register (High Word)
  AD1CTMUENH = 0;             // Unimplemented channels are read as ‘0’. 
  // AD1CTMENL: CTMU Enable Register (Low Word)
  AD1CTMUENL = 1 ;   // CTMU enable in AN0 channel
  

Üdv:  kenéz