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C:\Program Files\HI-TECH Software\PICC-18\PRO\9.65\include\pic18f45k20.h


// Configuration Bit Values


// Configuration register 1
// Internal/External Switch Over
 #define IESOEN  0x7FFF  // Internal/External switch over mode enabled
 #define IESODIS 0xFFFF  // Internal/External switch over mode disabled
// Failsafe Clock Monitor
 #define FCMEN  0xBFFF  // Fail-safe clock monitor enabled
 #define FCMDIS  0xFFFF  // Fail-safe clock monitor disabled
// Oscillator Selection
 #define EXTCLKO 0xF7FF  // External RC, RA6=CLKOUT
 #define RCCLKO  0xF1FF  // Internal RC, RA6=CLKOUT, RA7=IO
 #define RCIO  0xF0FF  // Internal RC, RA6=IO, RA7=IO
 #define EXTIO  0xFFFF  // External RC, RA6=IO
 #define HSPLL  0xFEFF  // HS with PLL enabled
 #define ECIO  0xFDFF  // EC, RA6=IO
 #define ECCLKO  0xFCFF  // EC, RA6=CLKOUT
 #define HS  0xFAFF  // HS osc
 #define XT  0xF9FF  // XT osc
 #define LP  0xF8FF  // LP osc

// Configuration register 2
// Brown-out Voltage Level
 #define BORV30  0xFFE7  // Brown out reset enabled, reset at 3.0V
 #define BORV27  0xFFEF  // Brown out reset enabled, reset at 2.7V
 #define BORV22  0xFFF7  // Brown out reset enabled, reset at 2.2V
 #define BORV18  0xFFFF  // Brown out reset enabled, reset at 1.8V
// Brown-out Detection
 #define BOREN  0xFFFF  // enabled in H'ware only (S'ware disabled)
 #define BOREN_XSLP 0xFFFD  // enabled in H'ware disabled in sleep
 #define SWBOREN 0xFFFB  // enabled and controlled by S'ware
 #define BORDIS  0xFFF9  // Brown out reset disabled
// Power-up Timer
 #define PWRTEN  0xFFFE  // enable
 #define PWRTDIS 0xFFFF  // disable
// Watchdog Prescaler
 #define WDTPS1  0xE1FF  // Watchdog timer enabled with prescaler(s)
 #define WDTPS2  0xE3FF
 #define WDTPS4  0xE5FF
 #define WDTPS8  0xE7FF
 #define WDTPS16 0xE9FF
 #define WDTPS32 0xEBFF
 #define WDTPS64 0xEDFF
 #define WDTPS128 0xEFFF
 #define WDTPS256 0xF1FF
 #define WDTPS512 0xF3FF
 #define WDTPS1K 0xF5FF
 #define WDTPS2K 0xF7FF
 #define WDTPS4K 0xF9FF
 #define WDTPS8K 0xFBFF
 #define WDTPS16K 0xFDFF
 #define WDTPS32K 0xFFFF
// Watchdog Timer
 #define WDTDIS  0xFEFF  // Watchdog timer under S'ware control
 #define WDTEN  0xFFFF  // included only for completeness

// Configuration register 3
// MCLR Pin Function
 #define MCLREN  0xFFFF  // MCLR pin enabled
 #define MCLRDIS 0x7FFF  // Disable MCLR
// HF Oscillator Fast Startup
 #define HFSTART 0xFFFF  // Faster startup - do not wait for HF osc to 
stabilize
 #define HFSTABLE 0xF7FF  // Wait for HF osc to stabilize before clocking 
CPU
// Low-power Timer 1 Oscillator
 #define LPT1EN  0xFBFF  // Timer 1 in low power configuration
 #define LPT1DIS 0xFFFF  // Timer 1 not in low power configuration
// Port B Analog/Digital Configuration
 #define PBANALOG 0xFFFF  // PortB<4:0> pins are analog on reset
 #define PBDIGITAL 0xFDFF  // PortB<4:0> pins are digital I/O on reset
// CCP2 Mux
 #define CCP2RC1 0xFFFF  // CCP2 is multiplexed on RC1
 #define CCP2RB3 0xFEFF  // CCP2 is multiplexed on RB3

// Configuration register 4
// Extended CPU Enable
 #define XINSTEN 0xFFBF  // Enable extended instruction set
 #define XINSTDIS 0xFFFF  // Disable extended instruction set (Legacy mode)
// Background Debug
 #define DEBUGEN 0xFF7F  // Debugger enabled
 #define DEBUGDIS 0xFFFF  // Debugger disabled
// Low Voltage Programming
 #define LVPEN  0xFFFF  // Low voltage ISP enabled
 #define LVPDIS  0xFFFB  // Low voltage ISP disabled
// Stack Overflow Reset
 #define STVREN  0xFFFF  // Stack over/underflow will cause reset
 #define STVRDIS 0xFFFE  // Stack over/underflow will not cause reset

// Configuration register 5
// Code Protection
 #define UNPROTECT 0xFFFF  // Do not protect memory
#if defined(_18F25K20) || defined(_18F26K20) || defined(_18F45K20) || 
defined(_18F46K20)
 #define CPA  0xFFF0  // Protect program memory sections
 #define CP3  0xFFF7  // Protect program memory block 3
 #define CP2  0xFFFB  // Protect program memory block 2
#else
 #define CPA  0xFFFC  // Protect program memory sections
#endif
 #define CP1  0xFFFD  // Protect program memory block 1
 #define CP0  0xFFFE  // Protect program memory block 0
 #define CPD  0x7FFF  // Protect EEPROM data
 #define CPB  0xBFFF  // Protect boot block
 #define CPALL CPA & CPB & CPD  // Protect all of the above

// Configuration register 6
// Write Protection
 #define WRTEN  0xFFFF  // Write enabled
#if defined(_18F25K20) || defined(_18F26K20) || defined(_18F45K20) || 
defined(_18F46K20)
 #define WPA  0xFFF0  // Write protect program memory sections
 #define WP3  0xFFF7  // Write protect program memory block 3
 #define WP2  0xFFFB  // Write protect program memory block 2
#else
 #define WPA  0xFFFC  // Write protect program memory sections
#endif
 #define WP1  0xFFFD  // Write protect program memory block 1
 #define WP0  0xFFFE  // Write protect program memory block 0
 #define WPD  0x7FFF  // Write protect EEPROM data
 #define WPB  0xBFFF  // Write protect boot block
 #define WPC  0xDFFF  // Write protect configuration registers
 #define WPALL WPA & WPB & WPC & WPD  // Write protect all of the above

// Configuration register 7
// Read Protection
#if defined(_18F25K20) || defined(_18F26K20) || defined(_18F45K20) || 
defined(_18F46K20)
 #define TRPA  0xFFF0  // Table read protect program memory sections
 #define TRP3  0xFFF7  // Table read protect program memory block 3
 #define TRP2  0xFFFB  // Table read protect program memory block 2
#else
 #define TRPA  0xFFFC  // Table read protect program memory sections
#endif
 #define TRP1  0xFFFD  // Table read protect program memory block 1
 #define TRP0  0xFFFE  // Table read protect program memory block 0
 #define TRPB  0xBFFF  // Table read protect boot block
 #define TRPALL TRPA & TRPB  // Table read protect all of the above