xilinx

[Tauri]

Hi Lista

2006. január 13., 18:49:08, írtad:

> Hali!

na most en vagyok repulo



ez lefordul nalad?

nalam a 92. sorban az "avr_pa" ertekadasaval van baj. ha kikomentezem
akkor fordul.



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ht is
    Port ( CLK : in std_logic;        
           ACLK : out std_logic;

 -- 8085 Lábak

           INTR : in std_logic;
           READY : in std_logic;
           RESETIN : in std_logic;
           RST55 : in std_logic;
           RST65 : in std_logic;
           RST75 : in std_logic;
           SID : in std_logic;
           TRAP : in std_logic;

           AD : inout std_logic_vector(7 downto 0);

           A8 : out std_logic;
           A9 : out std_logic;
                 A10 : out std_logic;
                 A11 : out std_logic;
                 A12 : out std_logic;
                 A13 : out std_logic;
                 A14 : out std_logic;
                 A15 : out std_logic;

           ALE : out std_logic;
           IOM : out std_logic;
           RD : out std_logic;
           WR : out std_logic;
           S0 : out std_logic;
           S1 : out std_logic;
           CLKOUT : out std_logic;
           HOLDA : out std_logic;

           INTA : out std_logic;
           RESOUT : out std_logic;
           SOD : out std_logic;

 -- AVR lábak

           AVR_RD : in std_logic;
           AVR_WR : in std_logic;
           AVR_ALE : in std_logic;
           AVR_PA : inout std_logic_vector(7 downto 0);
           AVR_PC : in std_logic_vector(7 downto 0);

 -- SRAM
                 raml: out std_logic_vector(7 downto 0);
                 ramh: out std_logic_vector(7 downto 0);
                 ramd: out std_logic_vector(7 downto 0);
                 ramcs: out std_logic;
                 ramoe: out std_logic;
                 ramwe: out std_logic;

                 RESET : in std_logic
                 );
end ht;

architecture Behavioral of ht is
signal O0: std_logic_vector(7 downto 0);
signal O1: std_logic_vector(7 downto 0);
signal O2: std_logic_vector(7 downto 0);
signal I0: std_logic_vector(7 downto 0);


signal aclks: std_logic;

begin

aclock: process(clk,reset)
begin
        if reset='L' then
                aclks<='0';
        elsif rising_edge(clk) then
                aclks<=not aclks;
        end if;
end process;

        O0<= avr_pa    when avr_pc="00000000" and rising_edge(avr_wr) and avr_rd='H';
        O1<= avr_pa    when avr_pc="00000001" and rising_edge(avr_wr) and avr_rd='H';
        O2<= avr_pa    when avr_pc="00000010" and rising_edge(avr_wr) and avr_rd='H';
        raml<= avr_pa  when avr_pc="00000011" and rising_edge(avr_wr) and avr_rd='H';
        ramh<= avr_pa  when avr_pc="00000100" and rising_edge(avr_wr) and avr_rd='H';
        ramd<= avr_pa  when avr_pc="00000101" and rising_edge(avr_wr) and avr_rd='H';

        avr_pa<="00000000" when avr_pc="00000000" and avr_rd='L' else "ZZZZZZZZ";

        aclk<=aclks;

-- 8085 outputok

        a8<=O0(0);
        a9<=O0(1);
        a10<=O0(2);
        a11<=O0(3);
        a12<=O0(4);
        a13<=O0(5);
        a14<=O0(6);
        a15<=O0(7);

        ale<=O1(0);
        iom<=O1(1);
        rd<=O1(2);
        wr<=O1(3);
        s0<=O1(4);
        s1<=O1(5);
        clkout<=O1(6);
        holdA<=O1(7);

        inta<=O2(0);
        resout<=O2(1);
        sod<=O2(2);

-- 8085 Inputok

        I0(0)<=intr;
        I0(1)<=ready;
        I0(2)<=resetin;
        I0(3)<=rst55;
        I0(4)<=rst65;
        I0(5)<=rst75;
        I0(6)<=sid;
        I0(7)<=trap;

end Behavioral;


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