VGA szinkron idők CPLD-ből
Horváth Vilmos
hovil at freemail.hu
Sat May 28 08:30:23 CEST 2005
VGA kimenetet szeretnék csinálni.
A netten találtam egy forrást, ami ugyan működik de vízszintes
visszafutások látszanak.
Le tudná valaki írni mikor is kell és mennyi ideig kiadni a szinkron
jeleket.
Csatoltam a forrást hátha valaki...
--------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demo is
Port (
clk : in std_logic;
hsync, vsync : out std_logic;
rgb : out std_logic_vector(2 downto 0);
end demo;
architecture Behavioral of demo is
-- VGA
subtype counter is integer range 0 to 1023;
subtype nibble is integer range 0 to 15;
-- constants for the timing of one scan line (# of dot clock cycles)
constant hsync_start : counter := 0;
constant hsync_end : counter := 94;
constant hscan_start : counter := 139;
constant hscan_end : counter := 780;
constant hline_end : counter := 800;
-- constants for the timing of one field (# of scan lines)
constant vsync_start : counter := 0;
constant vsync_end : counter := 1;
constant vscan_start : counter := 34;
constant vscan_end : counter := 514;
constant field_end : counter := 524;
-- global signals
signal dot_count, row_count : counter;
signal vgaclk: std_logic;
begin
-- VGA
with dot_count select
hsync <= '1' when hsync_start to hsync_end,
'0' when others;
with row_count select
vsync <= '1' when vsync_start to vsync_end,
'0' when others;
vgascan : process
begin
wait until rising_edge(clk);
-- compute waveform counter state
if dot_count < hline_end then
dot_count <= dot_count + 1;
else
dot_count <= 0;
if row_count < field_end then
row_count <= row_count + 1;
else
row_count <= 0;
end if;
end if;
-- compute rgb outputs
if dot_count > hscan_start and dot_count < hscan_end then
rgb <= "100";
else
rgb <= "000";
end if;
end process vgascan;
end Behavioral;
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