cpld globalis reset

Rado Zoltan zrado at leasingtechnology.com
Wed Sep 22 17:07:57 CEST 2004


Hello Babrian,

Monday, September 20, 2004, 9:33:56 AM, you wrote:

Naszóval akkor mindenki okulásául, öröméül:
Illetve majdnem mindenki ;-)
Szép napokat!

Zoli

---------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test1 is
    Port ( A : in std_logic;
           B : in std_logic;
           D : in std_logic;
           Q : out std_logic);
end test1;

architecture Behavioral of test1 is

SIGNAL inner_clk:       std_logic;

begin

inner_clk <= A AND B;

ff:process(inner_clk)
begin
        if inner_clk'event and inner_clk = '1' then
                Q <= D;
        end if;
end process ff;


end Behavioral;

-------------------
 UCF file:
-------------------

net inner_clk BUFG=CLK;
------------------------------------------------------------







More information about the Elektro mailing list