Xilinx coregen -> VHDL

[Szolnoki Tibor]

A CoreGenerator altal keszitett modult az FPGAExpress nem latja, hiszen az nem a VHDL forras resze. Egy kulon .edn fajlban van, ezt majd az implementacio soran kerul be a top-level modulba. Szerintem ez a Warning nem lenyeges. Persze implementalasnal az .edn fajlnak a project alkonyvtarban kell lennie.

Tipp:
1, A SpartanXL-hez boven eleg a LogiBLOX-is
2, 16 szohosszig meg ez sem kell, mert hasznalhatsz "primitive" componenst is. Van egy RAM16X1D alapkomponens. Ezt generalni sem kell, elvileg az FPGA Express-nek is ismernie kell. Viszont mivel 16x1 bites, ezert annyiszor kell hasznalni ahany adatbit hosszu kell. (Ha LogiBlox-ot, vagy CoreGen-t hasznalsz, az is ennyit hasnzal fel, ugyhogy semmit sem vesztel! 

Udv:
Tibi

  ----- Original Message ----- 
  From: Radó Zoltán 
  To: lista at chipcad.hu ; elektro at irisz.hu 
  Sent: Saturday, April 28, 2001 11:34 AM
  Subject: Xilinx coregen -> VHDL


  Haliho mindenkinek!

  Lenne egy problemam, amit nem tudok megoldani:
  Bocsanat mindenkitol a hosszu level miatt....
  Core generatorral generalt memoriablockot szeretnek hasznalni a VHDL kodban.
  A VHO filebol atmasoltam a componens definiciot es a hozzarendeleseket. A
  hozzarendeleseket modositottam a szuksegleteknek megfeleloen. A core
  SpartanXL-be Basic Element, Registered DualPort RAM. 16bit szeles 16 mely DP
  RAM.... A problema az, hogy a szintezis soran folyamatosan olyan warning-ot
  kapok, hogy:
   
  Warning: Cannot link cell 'OUTFIFO/dpramo' to its reference design 'dp16x16'. (FPGA-LINK-2)
   
  Mit kell meg beallitani? Vagy mi nem jo?
   
  Segitsegeket elore is koszi...
  Udv: Zoli


  A vhdl modul amiben hasznalnam:

  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;


  entity OUTFIFO is
      port (
       RESET: in STD_LOGIC;
          RD: in STD_LOGIC;
          WR: in STD_LOGIC;
          D: in STD_LOGIC_VECTOR (15 downto 0);
          Q: out STD_LOGIC_VECTOR (7 downto 0)
      );
  end OUTFIFO;

  architecture OUTFIFO_arch of OUTFIFO is


  SIGNAL RA: integer range 0 to 31;
  SIGNAL WA: integer range 0 to 31;
  SIGNAL EMPTY: std_logic;
  SIGNAL FULL: std_logic;
  SIGNAL STDWA: std_logic_vector(4 downto 0);
  SIGNAL STDRA: std_logic_vector(4 downto 0);
  SIGNAL kamu: std_logic_vector(15 downto 0);
  SIGNAL tmpq: std_logic_vector(15 downto 0);

  SIGNAL one: std_logic ;

  component dp16x16
   port (
   a: IN std_logic_VECTOR(3 downto 0);
   dpra: IN std_logic_VECTOR(3 downto 0);
   d: IN std_logic_VECTOR(15 downto 0);
   we: IN std_logic;
   c: IN std_logic;
   ce: IN std_logic;
   spo: OUT std_logic_VECTOR(15 downto 0);
   dpo: OUT std_logic_VECTOR(15 downto 0));
  end component;

  begin

  dpramo : dp16x16
    port map (
     a => stdwa(4 downto 1),
     dpra => stdra(4 downto 1),
     d => d,
     we => one,
     c => wr,
     ce => one,
     spo => kamu,
     dpo => tmpq(15 downto 0));

     sampmux: process(tmpq,stdra)

     begin
      if stdra(0) = '1' then
       q<= tmpq(7 downto 0);
      else
       q<= tmpq(15 downto 8);
      end if;
     end process;



     wrcount: process(wr,reset)

     variable wcnt: integer range 0 to 31;
     variable tmpSTDWA : std_logic_vector(4 downto 0);

     begin
      one <= '1';
      if RESET ='1' then
       wcnt:= 0;
       STDWA <= "00000";
       WA <= 0;

      elsif WR'event and WR ='0' then
       if FULL = '0' then
        wcnt:= wcnt +2;
        WA <= wcnt;
        STDWA <= conv_std_logic_vector(wcnt,5);

       end if;
      end if;
     end process;


     rdcount: process(rd,reset)

     variable rcnt: integer range 0 to 31;

     begin
      if RESET = '1' then
       rcnt:= 0;
       STDRA <= "00000";
       RA <= 0;

      elsif RD'event and RD = '0' then
       if EMPTY = '0' then
        rcnt:= rcnt +1;
        RA <= rcnt;
        STDRA <= conv_std_logic_vector(rcnt,5);
       end if;
      end if;
     end process;

     process(WA, RA)

     variable sub: integer range 0 to 31;

     begin

      SUB:= WA - RA;

      if SUB = 0 then
       EMPTY <= '1';
      else
       EMPTY <= '0';
      end if;

      if SUB = 31 or SUB = 30 then
       FULL <= '1';
      else
       FULL <= '0';
      end if;

     end process;

  end OUTFIFO_arch;


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